FIG. 1 illustrates a conventional PoDL system with a PSE 10 and a PD 12. The PSE 10 is shown as excluding the various AC and DC filters and the master PHY 16 (physical layer); however, the PSE 10 may alternatively be designated as including all of the circuitry on the left side of the twisted wire pair 14. The master PHY 16 is a transceiver containing conventional circuitry (e.g., transformers, amplifiers, conditioning circuits, etc.) that receives and transmits the relatively high speed Ethernet differential data and ensures that the data signals have the proper characteristics in accordance with the IEEE802.3 physical layer standards for T1 Ethernet.
The PSE 10 controls the coupling of the DC voltage VIN, generated by a voltage source, to the PD 12.
The Ethernet differential data may be generated and received by a host processing system that may be considered part of the PSE 10.
The PD 12 is shown as excluding the various AC and DC filters and the slave PHY 18; however, the PD 12 may alternatively be designated as including all of the circuitry on the right side of the twisted wire pair 14. The slave PHY 18 may be identical to the master PHY 16 and is powered by the DC voltage VIN transmitted by the PSE 10. The Ethernet differential data on the PD side may be generated and received by a slave processing system that may be considered part of the PD 12. The PD 12 may contain a DC/DC converter for converting the incoming voltage to a target voltage VOUT. The VOUT may be used only to power the PD 12 and slave PHY 18 or may be used to power additional equipment. The DC voltage range supplied by the PSE 10 is dictated by the IEEE802.3bu standard.
The capacitors CPSE and CPD smooth the voltages VIN and VOUT.
The inductors L1, L2, L3, and L4 pass DC but block the Ethernet AC differential data, and the capacitors C1, C2, C3, and C4 pass the AC differential data but block DC. The various inductors and capacitors are referred to as a coupling/decoupling network since they couple the DC and AC to the wire pair 14 and decouple the DC and AC from the wire pair 14.
The PoDL system includes circuitry in the PSE 10 and PD 12 that performs a detection and classification routine before the PSE 10 can couple the DC voltage VIN to the wire pair 14. The detection and classification signals must be transmitted/received via the coupling/decoupling network. The requirements for detection and classification schemes for PoDL preclude re-using the schemes used for the much older Power over Ethernet (PoE). In PoE, at least two wire pairs in the standard CAT-5 cable are used to transmit the DC voltage and conduct the differential data signals. In a conventional PoE system, a PSE controls the magnitudes of current-limited signals on the wire pairs that are directly used by a PD to power the PD and generate a characteristic response that conveys PoE-related characteristics of the PD. Very limited information can be communicated using this conventional PoE technique. Only after the PD has conveyed that it is PoE-compatible, can the PSE couple the DC voltage source to the wire pairs to fully power the PD.
What is needed is an improved low-current detection and classification scheme for a PoDL system that can be used to rapidly convey any desired information prior the full DC voltage being coupled across the wire pair. This new detection and classification scheme specifically for use with PoDL should make use of the differences between PoDL (one wire pair) and PoE (two wire pairs).